The present invention relates to techniques of logic emulation constituting one of the processes for developing integrated circuits. More particularly, the invention relates to a logic emulation module and a logic emulation board for carrying out logic emulation efficiently.
Heretofore, there were techniques of software emulation (logic simulation) designed to improve accuracy in logically verifying logic elements that make up large-scale integrated circuits (LSI) for use in information processing equipment. Such software emulation techniques have since been supplemented by techniques of hardware emulation (logic emulation) that utilize FPGAs (field programmable gate arrays) forming programmable LSI. Logic emulation involves programming, by use of a plurality of FPGAS, a pseudo-LSI device that emulates the logic of a target LSI to be designed (i.e., targeted for logic verification) and generating the programmed pseudo-LSI for checks on its logical performance. One such logic verification device is disclosed illustratively in Japanese Published Unexamined Patent Application No. Hei 6-3414.
Large-scale integrated circuits targeted for development come most often in the form of a multi-chip module or a CSP (chip size package). A multi-chip module is made up of a plurality of LSI chips mounted in bare fashion on a board. A CSP is constituted by a bare chip mounted on a board called a carrier, the chip being soldered onto the board by ball bonding.
Any LSI under development and its corresponding FPGA differ in package sizes, connecting structures and pin assignments. To overcome the differences requires newly designing a logic verification board that will carry the FPGA intended for logic emulation. Package of FPGAs are generally structured as PGA (pin grid array), QFP (quad flat package) or BGA (ball grid array). To combine a plurality of FPGAs thus requires constructing an emulation device wherein the board for carrying the arrays is sufficiently enlarged or wherein the arrays are logically divided into a plurality of boards to be connected by means of a back plane board. In such cases, appropriate connecting means must be provided between the emulation device and the logic board that bears the LSI being developed.
It is therefore an object of the present invention to provide a logic module for logic verification and a logic emulation device, whereby the number of logic emulation steps is reduced.
It is another object of the present invention to provide a logic module for logic verification and a logic emulation device, such that there is no need to design a logic verification board anew.
It is a further object of the present invention to provide techniques for implementing efficient cooling of a multi-chip module through heat conduction.
In carrying out the invention and according to one aspect thereof, there is provided a logic module comprising: a board; at least one FPGA and at least one switching LSI mounted on at least one side of the board, the FPGA allowing internal gates to be programmed for logic implementation, the switching LSI permitting circuit interconnections to be programmed; connectors attached to the board for electrical connection with the outside; board wiring for directly connecting the FPGA to the connectors; and board wiring for coupling the FPGA to the connectors by way of the switching LSI.
According to another aspect of the invention, there is provided a logic board targeted for logic verification, comprising: connectors for connection with logic modules; and terminal lands on which to mount LSIs to be developed; wherein the connectors and the terminal lands are interconnected on a one-to-one basis.
A logic module has its connectors coupled to those of the logic board so that the module is mounted on the board targeted for verification. The logic board, on which an LSI to be developed is to be actually mounted, is thus prepared for logic verification. After the verification, the logic module may be dismounted from the logic board and the target LSI may be mounted on the board for evaluation.
If an FPGA is needed, two or more logic modules of the above type may be stacked connectively through external-coupling connectors of the modules. This multiple-stage logic module arrangement makes it possible to expand the logic scale per unit packaging area.
If the number of external terminals for LSIs mounted on one side of a logic module differs from the external terminal count on the other side, boards called LSI carriers may be used to arrange the terminal assignments into an identical land layout on both sides. With the two sides of the logic module having the same land layout, through-holes alone on the logic module board may be used to connect the identically located signal terminal lands, power supply lands and ground terminal lands. This provides a considerable improvement in the ease of design.
Preferably, radiation plates may be attached to four corners of the inventive logic module with metal spacers interposed therebetween. Between the radiation plates on the one hand and various LSIs such as FPGAs and switching LSIs attached to the logic module on the other hand, there may be provided heat conduction sheets that elastically conform to and snugly contact the shapes of these LSIs. Heat from the LSIs is dissipated through the heat conduction sheets and radiation plates. Because the heat conduction sheets elastically follow the LSI contours, LSIs of different heights mounted on the same board surface may still have their different elevations covered by the sheets. Since the radiation plates are attached to the four corners of the logic module with metal spacers interposed, it is possible to implement a cooling structure that will not interfere with component layout and wiring design.
If a plurality of logic modules are stacked connectively, the heat from a lower-stage logic module may be thermally conducted through the flexibly bending heat conduction sheets to the radiation plates of an upper-stage logic module. The structure permits efficient cooling of the multiple-stage logic module setup.
Other objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings.